CQ Publishing FPGA magazine no. Ten

Speaking of FPGA development, it is common to describe the source code of RTL (Resister Transfer Level) in HDL (Hardware Description Language) such as Verilog HDL and VHDL, and perform logic synthesis with the development tools of FPGA vendors. As the name suggests, RTL description in HDL is a language for describing hardware operations such as register transfer, and logic synthesis of algorithms with a higher degree of abstraction is not possible. For this reason, a higher-level (higher) level description method was desired. As you know, C language is often used in software development. If the hardware can be designed in C language, which is good at describing algorithms, it can be expected that development will be very easy. From such a flow, a high-level synthesis tool corresponding to C language has appeared. This document describes the development of a mixed hardware / software system using Xilinx's latest development tools SDSoC and Vivado HLS, and a design example of an image filter system realized by Altera's Nios II and the high-level synthesis tool eXCite. In addition, we will explain how to convert from C language source to Verilog HDL using the free next-generation compiler LLVM and drop it into FPGA. We compare and consider the circuit scale and operating frequency caused by the difference in the specification of optimization options during conversion. In addition to C language, we also introduce examples of developing FPGAs with OpenCL and examples of writing hardware with Java as special articles.